Low Power Codec with Class D Speaker Driver

The CS42L52 is a 24-bit, low power stereo audio codec providing up to 1 W per channel of highly efficient Class D amplification to external speakers, or enough power to drive 44 mW per channel into stereo headphones and consumes only 13 mW of power at 1.8 V in playback mode. The CS42L52 offers the flexibility to run its core from a single power supply and directly connect the Class D amplifier to the battery supply for a more efficient operation. With its ground-centered outputs, the CS42L52 helps to reduce clicks and pops during start up, improves low-end frequency response and eliminates costly, space-consuming DC blocking capacitors.

Product Categories

Smart Home, Wearables

Features

Stereo Codec:

  • High performance stereo ADC & DAC
    • 99 dB (ADC),98 dB (DAC) dynamic range (A-wtd)
    • -88 dB THD+N
  • Flexible stereo analog input architecture
    • 4:1 analog input MUXr
    • Analog input mixing
    • Analog pass-thru with volume control
    • Analog Programmable Gain Amplifier (PGA)
  • Programmable Automatic Level Control (ALC)
    • Noise gate for noise suppression
    • Programmable threshold & attack/release rates
  • Dual MIC inputs
    • Differential or single-ended
    • +16 dB to +32 dB w/1 dB step MIC pre-amplifiers
    • Programmable, low noise MIC bias levels
  • Digital signal processing engine
    • Bass & treble tone control, de-emphasis
    • Master Vol. and independent PCM SDIN + ADC SDOUT Mix Vol. Ctl.
    • Soft-ramp & Zero-cross transitions
    • Programmable peak-detect and limiter
    • Beep generator w/full tone control

Class D Stereo/Mono Speaker Amplifier:

  • No external filter required
  • High stereo output power at 10% THD+N
    • 2 x 1.00 W into 8 Ω @ 5.0 V
    • 2 x 550 mW into 8 Ω @ 3.7 V
    • 2 x 230 mW into 8 Ω @ 2.5 V
  • High mono output power at 10% THD+N
    • 1 x 1.90 W into 4 Ω @ 5.0 V
    • 1 x 1.00 W into 4 Ω @ 3.7 V
    • 1 x 350 mW into 4 Ω @ 2.5 V
  • Direct battery powered operation
    • Battery level monitoring & compensation
  • 82% at 800 mW
  • Phase-aligned PWM output reduces idle channel current
  • Spread spectrum modulation
  • Low quiescent current

Stereo Headphone Amplifier:

  • Ground centered outputs
    • No DC-blocking capacitor required
    • Integrated negative voltage regulator
  • High power output at -75 dB THD+N
    • 2 x 23 mW into 16 Ω @ 1.8 V
    • 2 x 44 mW into 16 Ω @ 2.5 V

System Features:

  • 12, 24, and 27 MHz master clock support in addition to typical audio clock rates
  • High performance 24-bit converters
    • Multi-bit Delta Sigma architecture
    • Very low 64Fs oversampling clock reduces power consumption
  • Low power operation
    • Stereo analog passthrough: 10 mW @ 1.8 V
    • Stereo playback: 14 mW @ 1.8 V
    • Stereo record and playback: 23 mW @ 1.8 V
  • Variable power supplies
    • 1.8 V to 2.5 V digital & analog
    • 2.5 V to 5 V Class D amplifier
    • 1.8 V to 2.5 V headphone amplifier
    • 1.8 V to 3.3 V interface logic
  • Power down management
    • ADC, DAC, codec, MIC pre-amplifier, PGA, headphone amplifier, speaker amplifier
  • Analog & digital routing/mixes:
    • Line/headphone out = analog in (ADC bypassed)
    • Line/headphone/speaker out = ADC + digital in
    • Digital out = ADC + digital in
    • Internal digital loopback
    • Mono mixes
  • Flexible clocking options
    • Master or slave operation
    • High impedance digital output option (for easy MUXing between codec & other data sources)
    • Quarter-speed mode - (i.e. allows 8 kHz Fs while maintaining a flat noise floor up to 16 kHz)
    • 4 kHz to 96 kHz sample rates
  • I²C control port operation
  • Temperature monitor & shutdown
  • Headphone/speaker detection input
  • Pop and click suppression

Parametric Specifications

DACs 2
ADCs 2
DAC THD+N (dB) -86
ADC THD+N (dB) -88
Sample Rate (kHz) 4-96
Analog Power Supply (V) 1.65-2.83
Supply Current (µA) 1.65-2.83
Package 40 QFN

Technical Documents

CS42L52 Product Data Sheet

Mar 11, 2013, DS680F2 : 3359 Kb

Errata: CS42L52 Rev B0 Silicon

Aug 24, 2007, ER680B1 : 99 Kb

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