Reliability and Qualification

From product development to product delivery, achieving the highest levels of product quality and reliability is our most important goal.

Quality Standards

Cirrus Logic's reliability program

Cirrus Logic strives to achieve the highest quality and reliability performance on all our products through a systematic approach. We emphasize quality and reliability at every phase of the product: from product design and development, fabrication, assembly, testing and out-going quality control. Our qualification and reliability testing is used to ensure all the products are below targets set for Early Failure Rates in PPM and Wear-Out Failures in FITs.

Process

Our approach to reliability

Reliability is the probability that a device performs its required function under stated conditions for a designated period of time. We build in quality and reliability at every phase: design, fabrication, assembly, test, and outgoing quality control.

What reliability means
The proportion of devices in service from time zero that will not have failed by a given time t.
A systematic approach
Quality and reliability are emphasized across design, fab, assembly, testing, and outgoing quality control.
Below target failure rates
Qualification and reliability testing keeps products below set targets for Early Failure Rates (PPM) and Wear-Out Failures (FITs).

bathtub curve

Types of failure over a product's life

The bathtub curve is a standard way to picture the types of failures during a device’s life time. There are two basic types of failures: Early Failures and Wear-Out Failures. Under normal device operation, there will be a low failure rate, consistent throughout its life.

failure analysis

How we measure failure rate

Failure rate expresses the probability that a device which was good until a given time fails in the next instant. Cirrus Logic uses several complementary measures.

Percentage

Failed devices ÷ total samples, expressed as a percentage.

FITs

Failures in time per billion (10⁹) device hours.

DPM (DPPM)

Defective parts per million devices.

Confidence interval

χ² weighting at a chosen level (typically 60%); useful when zero failures occur in limited samples.

testing

Categories of reliability testing

Reliability tests are performed for fab, technology, packages, and assemblies in two distinct ways.

Qualification

New products are tested for manufacturability before release, across fab, technology, packages, and assemblies.

Monitoring

Existing devices are periodically re-tested to confirm manufacturability stays at a high standard of reliability and quality.

testing

Reliability Stress Tests

The typical stress tests performed by Cirrus Logic. Devices must pass the same electrical and functional testing throughout; failure analysis identifies root cause and drives corrective action.

Note: The stresses shown reflect typical test conditions. Exact temperature ranges, cycle counts, and test durations vary by customer and market segment, with testing spanning temperatures from −65°C to 150°C and up to 1,000 cycles.

stress test

Purpose & conditions

Operating Life (JEDEC JESD22-A108)

Uses temperature and dynamic voltage biasing to accelerate failure mechanisms. Infant/Early Life testing estimates the early failure rate (DPM) over the first 3 to 6 months as a measure of the fabrication process. High Temperature Operating Life (HTOL), typically performed at 125°C and maximum datasheet bias, evaluates resistance to prolonged electrical and thermal stress. Low Temperature Operating Life (LTOL) applies biased stress at lower temperatures, typically −40°C, to assess hot-carrier degradation.

Preconditioning – Precon (JESD22-A113 / IPC/JEDEC J-STD-020)

Simulates the real-life PC-board assembly process (dry bake, moisture soak, and solder-reflow simulation with ATE testing) performed prior to package qualification tests (HAST/THB, TC, UHAST). Conditions: bake 125°C, moisture soak 30°C / 60%RH, reflow 260°C.

Biased Highly Accelerated Stress Test – HAST (JESD22-A110)

Simulates extreme operating conditions (similar to THB). Devices are stressed with bias at high temperature and humidity, then ATE-tested for electrical failures. Conditions: 130°C or 110°C, 85%RH, 96 or 264 hours, with voltage bias.

Temperature Humidity Bias – THB (JESD22-A101)

Determines device/package resistance to prolonged temperature, humidity, and electrical stress, with maximum differential bias on alternating pins, then ATE testing. Conditions: 85°C, 85%RH, 1000 hours (interim reads at 100 and 500 hours), with voltage bias.

Temperature Cycle – TC (JESD22-A104)

Accelerates thermal-expansion mismatch among package and circuit materials to determine resistance to temperature extremes and changes during transport and use; failed parts are checked for stress cracks and delamination. Conditions: +150°C to −65°C, 10 minutes per chamber, 500 cycles.

Unbiased Highly Accelerated Stress Test – UHAST (JESD22-A118)

Simulates extreme operating conditions (similar to Autoclave). Devices are stressed at high temperature and humidity, then ATE-tested for electrical failures. Conditions: 130°C or 110°C, 85%RH, 96 or 264 hours.

High Temperature Storage Life – HTSL (JESD22-A103)

Determines the effect of time and temperature under storage conditions for thermally activated failure mechanisms. Devices are baked, then ATE-tested for electrical failures. Conditions: 150°C, 1000 hours.

Low Temperature Storage Life – LSTL (JESD22-A119)

Determines the effect of time and temperature under low-temperature storage conditions. Devices are stored at low temperature, then ATE-tested for electrical failures. Conditions: −40°C, 1,000 hours.

Moisture Sensitivity Level – MSL (JEDEC J-STD-020)

Classifies how much moisture a surface-mount package can absorb before reflow soldering without cracking or delaminating. The resulting classification establishes the product’s handling requirements, including whether dry packing is required.

Electrostatic Discharge – ESD (JS-001 / JESD22-C101)

Determines a device’s ESD sensitivity using the Human Body Model (HBM, JS-001), which models discharge into a pin from a statically charged human body (C=100pF, R=1.5kΩ), and the Charged Device Model (CDM, JESD22-C101), which models discharge from a charged package/lead frame contacting a metal fixture.

Electrostatic Discharge – Charged Device Model (CDM) (JS-002)

Evaluates a device’s resistance to electrostatic discharge when charge accumulated on the device is rapidly released through contact with a grounded conductor. Devices are classified according to the voltage level they withstand.

Latch-Up (JEDEC 78)

Verifies a device can withstand SCR latch-up from DC current injected into input and I/O pins, as well as power-supply overvoltage; parts must pass ATE testing after stress. Conditions: I/O injection ±0 to 100 mA and Vdd at 1.5 × Vdd(max), at 25°C or the max specified temperature.

testing

Board-Level Reliability (BLR)

For advanced and emerging package technologies, board-level reliability testing evaluates solder-joint interconnect reliability using daisy-chained test vehicles. Failure analysis on failed samples determines the cause.

stress test

Purpose

Thermal Cycle – BLR TC (JESD22-A104 / IPC-9701)

Accelerates thermal-expansion mismatch between the component solder joint and the system board; daisy-chain resistance is measured in-situ or at read points and compared to the initial value. Conditions: +85°C to −40°C, ~60 minutes per cycle, 1000 cycles.

Mechanical Shock – BLR MS (JESD22-B110 / B111)

Evaluates shock performance of the board-mounted component to simulate handling, transport, and field-operation failure modes; daisy-chain resistance is measured at read points and compared to the initial value. Conditions: half-sine pulse, peak 1500G or 2900G with PCB bending, 30 shocks.

Explore our quality program

The Cirrus Logic quality program spans our fabless operating model, product development, reliability qualification, failure analysis, supplier and customer quality, management systems, and corporate compliance.

Product Development
From initial design through production, quality is built into every stage of our product development process.
Reliability and Qualification
Rigorous qualification and ongoing monitoring help ensure reliable, high-quality products throughout their lifecycle.
Failure Analysis
Remediate errors faster with our in-house Device Physics Lab and extensive failure analysis expertise.
Supplier Management
Learn how we qualify, audit, and monitor manufacturing partners across our supply chain.

Customer Management
Find out how our teams manage quality concerns, communication, and customer support.
ISO Management Systems
Review our ISO-certified quality and environmental management systems, standards, and practices.
Fabless Semiconductor Model
See how we maintain quality across foundry, assembly, test, and production partners.
Product Longevity
See how we support 10+ year product lifecycles through resilient supply planning and strong manufacturing partnerships.