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Cirrus Logic Reliability: Qualification & Monitoring

Memberships and Certifications

Cirrus Logic is a member of industry standard and quality professional organizations. We actively participate in industry standard development as part of AEC, JEDEC and AIAG members.

  1. AEC Web page
  2. JEDEC Web page

Reliability and Qualification Test Description

  1. What is Reliability?

    Reliability is the probability that an item will perform the required function under stated conditions for a designated period of time. Reliability in semiconductor devices is, in two words, the Survival Rate. It is the proportion of devices used from time zero that will not have failed by a given time ‘t’.

  2. Cirrus Logic Quality and Reliability

    Cirrus Logic strives to achieve the highest quality and reliability performance on all our products through a systematic approach. We emphasize quality and reliability at every phase of the product: from product design/development, fabrication, assembly, testing and out going quality control. Our qualification/reliability testing is used to ensure all its products are below targets set for Early Failure Rates in PPM and Wear-Out Failures in FITs.

  3. Reliability Failures

    The bathtub curve is a standard way to picture the types of failures during a device’s life time. There are 2 basic types of failures, Early Failures and Wear-Out Failures. During the normal operation of the device operation, that is the section between early failures and wear out, the failure rate is normally constant and at an extremely low rate.

    Bathtub Curve
    Figure: Bathtub curve, failure rates during
    the life time of a product.
    (Click to expand)

  4. Cirrus Logic Reliability Categories

    Cirrus Logic reliability tests can be divided into two categories: qualification and monitoring.

    1. Qualification:
      • Purpose: New products are tested for manufacturability.
      • Performed for fab, technology, packages, and assemblies.
    2. Monitoring:
      • Purpose: Existing devices are periodically tested to ensure manufacturability remains at a high standard of Reliability and Quality.
      • Performed for fab, technology, packages, and assemblies.
  5. What is a Failure Rate?

    Failure rate is a typical measure of reliability. It expresses the degree of probability that a device which was “good” until a given time and will fail in the next instant. The measures used at Cirrus Logic to describe a device’s reliability are:

    1. Percentage: number of device failed divided by the total number of samples in consideration expressed in percentage.
    2. FITS (Failure in time per billion device hours): the number of defects per 109 samples.
    3. DPM (DPPM): the number of defects (defect parts) per million devices.
    4. Confidence interval: χ 2 with a chosen confidence level (normally, 60%) is used as a weight in calculating failure rates. It is especially useful when zero failures observed in the limited sample sizes.

Reliability Stress Test Description

The following is a list of the typical stress tests performed by Cirrus Logic.

Test conditions follow Cirrus Logic Integrated Circuit Qualification Specifications, applicable JEDEC standard, or AEC Q100. Wherever conflicts arise, JEDEC is followed for commercial product and AEC is followed for automotive products.

Devices which undergo the following stress tests are required to pass the same electrical and functional test throughout. Failure analysis is required and root of causes should be identified and corrective actions followed as necessary.

  1. Operating Life (JEDEC JESD22-A108)

    Operating life is an intense stress test performed to accelerate thermally activated failure mechanisms through the application of extreme temperature and dynamic biasing conditions. Typically it is performed at 125°C with a bias level at the maximum data sheet specifications.

    1. Infant Life

      Failure rate is higher during the initial use due to random defects, the variation of the production process, etc. Infant/Early life test is performed to estimate the failure rate, usually measured by DPM, during that period of time (3 month to 6 months). Infant life test is normally a reliability measure to the fab process used for the device. Early failure rate (EFR) is controlled by production burn-in or Vbump stress until the design and/or fab process is made more robust.

      Purpose: a continuous voltage (device specific) is applied to the device at 125°C for various lengths of time. Infant mortality rates or early failure rates are calculated and the length of production burn-in is determined from the results of the test.

      Description: conditions of maximum VSSs, I/O loading, clock rate vectors applied to exercises maximum amount of digital circuitry, and appropriate stimulus to exercises analog full scale ranges applied to the device at 125°C for various lengths of time.

      Vbump testing is a method to screen out weak parts by providing a higher than normal supply voltage for a short period of time.

      Results: typically measure in DPM

    2. High Temperature Operating Life (HTOL)

      The operating life failure rate period generally continues for a considerably longer time. HTOL is used to determine device resistance to prolonged operating stress, including both electrical and thermal mechanism. HTOL is normally a reliability measure for the design/layout of the device in a given fab process.

      Purpose: to simulate the operating lifetime under a specified set of conditions.

      Description: same as Infant life.

      Results: Measured in FITs.

      Preconditioning

      Purpose: to simulate “real life” PC board assembly process. This stress is performed prior to package reliability qualification and monitoring tests. Preconditioning are performed before THB, TC, TS, and Autoclave as well HAST tests.

      Bake

      Soak (JESD22-A113)

      • Reflow (devices under go either IR reflow or VPR or flux immersion) (J-STD-020)
      • Flux Immersion

  2. Biased Highly Accelerated Stress Test (HAST) (JESD22-A110)

    Purpose: to simulate extreme operating conditions. (Very similar to THB).

    Description: Devices are baked in a chamber at an extreme temperature and humidity for various lengths of time. The devices are subjected to bias while the devices are in the chamber. The devices are then ATE tested for electrical failures.

    Variables: Temp = 130°C / Humidity = 85% RH/ Time = 96 hours, voltage bias levels.

    Results: Measured in % defective.

  3. Temperature Humidity Bias (THB) (JESD22-A101)

    Purpose: to determine device/package resistance to prolonged temperature, humidity, and electrical stress.

    Description: Devices are baked in an oven at extreme temperature and humidity for various lengths of time. The devices are subjected to maximum differential bias on alternating pins while the devices are in the oven. The devices are then ATE tested for electrical failures.

    Variables: Temp = 85°C / Humidity = 85% RH / Time = 1000 hours (interim readpoints are 100 and 500 hours), voltage bias levels.

    Results: Measured in % defective.

  4. Pressure Pot (PPOT) (Autoclave) (JESD22-A102)

    Purpose: testing moisture resistance of plastic encapsulated devices.

    Description: Devices are baked in an autoclave (on a tray) at high temperatures and humidity for an extended period of time under static conditions. An ATE test is performed after the autoclave. Failed devices are checked for delamination, shorts, broken wires, etc.

    Variables: Temp = 121°C / Pressure = 15 Psi / Humidity = 100 % RH / Time = 96 hours

    Results: Measured in % defective.

  5. Temp Cycle (TMCL) (JESD22-104)

    Purpose: typically accelerates the effects of thermal expansion mismatch among different components of the package and circuit. It is used to determine package resistance to high and low temperature and to temperature changes during transportation and use.

    Description: Devices are placed in a receptacle within a vertical tube with two chambers full of air. The top chamber is heated and the bottom is cooled. The devices are moved from one chamber to the other alternately. The devices are ATE tested afterwards. Failed devices are checked for stress cracks on injection molding or epoxy used for die mounting, delamination, etc.

    Variables: Temp = 150°C (top) and -65° C (bottom) / Time = 10 minutes per chamber, number of cycles = 500.

    Results: Measured in % defective

  6. Unbiased Highly Accelerated Stress Test (UHAST) (JESD22-A118)

    Purpose: to simulate extreme operating conditions. (Similar to Autoclave).

    Description: Devices are baked in a chamber at an extreme temperature and humidity for various lengths of time. The devices are then ATE tested for electrical failures.

    Variables: Temp = 130°C / Humidity = 85% RH/ Time = 96 hours

    Results: Measured in % defective.

  7. HTSL (JESD22-A103)

    Purpose: Used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices.

    Description: Devices are baked in a chamber at an extreme temperature and humidity for various lengths of time. The devices are then ATE tested for electrical failures.

    Variables: Temp = 150°C / Time = 1000 hours

    Results: Measured in % defective.

  8. ESD

    This stress is used to determine the Electrical Static Discharge (ESD) sensitivity for a semiconductor device. The following are three commonly used models of tests.

    ESD test types:

    1. Human body model (HBM) (JESD22-A114)

      Models the discharge of electricity into a pin on a device through contact with a human body that has been charged with static electricity. Equivalent capacitance of the discharge circuit C=100pF and resistance R=1.5 km.

    2. Machine model (MM) (JESD22-A115)

      Models the discharge of electricity that occurs when a charged metal apparatus contacts a pin on a device. With low discharge resistance, a high discharge current is releases, increasing probable breakdown of the device. Equivalent capacitance of the discharge circuit C=200pF and resistance R= 0 m.

    3. Charged device model (CDM) (JESD22-C101)

      Models the discharge of electricity which occurs after an area such as the device package or lead frame becomes charged due to handling, and a pin on the device then contacts a metal apparatus or fixture. It has been found that this model shows good correlation with the breakdown mode on automatic assembly lines.

  9. Latch-UP (JEDEC 78)

    Latch-Up testing performed to ascertain whether a device can sustain SCR latch-up due to DC current injected into the input and I/O pins (and/or supply, which is not currently performed at Cirrus Logic). Current injections as well as power supply over voltage are tested at Cirrus Logic.

    Latch-UP I/O:

    Variables: Injection current +-(0 to 100) mA, temperature, 25°C or high max of the specified temperature on data sheet.

    Measure: pass Automated Test Equipment (ATE) after subjected to all input and I/O injection of +-100 mA.

    Sample size: 6 devices each from 1 lot.

    Results: zero devices should fail ATE test.

  10. Latch-UP Vdd

    Variables: Power supply tested at 1.5*Vddmax, temperature, 25°C or high max of the specified temperature on data sheet.

    Measure: pass ATE after subjected to all input and Vdd power swing.

    Sample size: 6 devices each from 1 lot.

    Results: zero out of the each five devices should fail ATE test.

  11. Solderability (JESD22-B102)

    Purpose: To determine the solderability of terminals after transportation and storage.

    Description: Devices are dipped in solder (or Pb-free) bath for a predetermined time. Testing is performed after steam and/or hot aging (preconditioning).

    Variables: Solder bath temperature: 245 +/-5 °C, Dip time: 5 +/- 0.5 s. Solder composition: Pb: Sn = 4:6, used with rosin flux.

    ** Pb free alloys for lead free package.

    Results: At least 95% of the immersed area must be coated with solder.

 
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