CS61584A

3.3 V and 5 V Dual T1/E1 Line Interface Unit

Overview

Power Supply (V)	Control Modes	Line Coders	Number of Channels	TBR-12 Compliant	Impedance Matching Line Driver	Arbitrary Waveform Option	Package
3.3 or 5	Host & H/W	AMI, B8ZS & HDB3	2				68 PLCC 64 LQFP

Description

The CS61584A is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. The device is optimized for flexible microprocessor control through a serial or parallel host mode interface. Hardware mode operation is also available.

Matched-impedance drivers reduce power consumption and provide substantial transmitter return loss. The transmitter pulse shapes are customizable to allow non-standard line loads. Crystal-less jitter attenuation complies with most stringent standards. Support of JTAG boundary scan enhances system testability and reliability.

Features

• Crystal-less jitter attenuator meets European CTR 12 and ETSI ETS 300 011 specifications
• Matched-impedance transmit drivers
• Transmitter High-Z capability
• Common transmit and receive transformers for all modes
• Serial and parallel host mode operation
• User-customizable pulse shapes
• Supports JTAG boundary scan
• Compliant with
• ITU-T Recommendations: G.703, G.704, G.706, G.732, G.775 and I.431
• ANSI: T1.102, T1.105, T1.403, T1.408, and T1.231
• FCC Rules and Regulations: Part 68 and Part 15
• AT&T Publication 62411
• ETSI ETS 300 011, 300 233, CTR 12, TBR 13
• TR-NET-00499
• 3.3 V and 5 V versions
• Package: 68-pin PLCC, 64-pin TQFP; lead-free assembly

Diagram

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