CS2000 Family

Clock Generation and Multiplication/Jitter Reduction Solution

Overview

Host Interface	One-Time- Programmable	Frequency Synth/ Clock Generator	Clock Multiplier/ Jitter Remover	Power Supply (V)	Input Frequency Range	Reference Frequency Range	Output Frequency Range	Package
CS2000
(CS2000-CP)	(CS2000-OTP)			3.3	50 Hz to 30 MHz	8 to 75 MHz	6 to 75 MHz	10 MSOP
CS2100
(CS2100-CP)	(CS2100-OTP)	—		3.3	50 Hz to 30 MHz	8 to 75 MHz	6 to 75 MHz	10 MSOP
CS2200
(CS2200-CP)	(CS2200-OTP)		—	3.3	—	8 to 75 MHz	6 to 75 MHz	10 MSOP
CS2300
(CS2300-CP)	(CS2300-OTP)	—		3.3	50 Hz to 30 MHz	Internally Generated	6 to 75 MHz	10 MSOP

Description

Featuring both a clock generator and clock multiplier/jitter reduced clock frequency synthesizer (clean up), Cirrus Logic’s CS2000 is a strong entrant into the clocking IC market. Based on an innovative hybrid analog-to-digital phase lock loop, the CS2000 gives system designers a unique solution for solving the complex challenges of clock generation and multiplication/jitter reduction.

The members of the CS2000 product family are differentiated by the method of control and/or a hardware mode configuration. The CS2000-CP is controlled via an I²C® / SPI™ control port and supports the full functionality of the CS2000. The CS2000-OTP is controlled in hardware mode via three mode pins. The functionality of the eight selectable modes is user defined and configured via the one-time-programmable feature.

The CS2xxx is a growing family of products based on the CS2000 and configured by Cirrus Logic to support common system requirements. Please contact Cirrus Logic for factory configuration of the CS2000 to support your unique requirements.

Features

• High-performance analog/digital phase locked loop
• Clock multiplier/jitter reduction
• Generates a low-jitter 6 – 75 MHz output clock from a jittery or intermittent 50 Hz to 30 MHz clock source
• Clock generation/frequency synthesis
• Generates a low-jitter 6 – 75 MHz clock relative to 8 – 75 MHz reference clock
• Highly accurate PLL multiplication factor
• Less than 1 PPM error
• Flexible control options
• One-time-programmable configuration for hardware mode
• I²C® / SPI™ control port
• Configurable auxiliary output
• Buffered reference clock
• PLL Lock indication
• Second PLL output
• Buffered version of CLK_IN
• Flexible sourcing of reference clock
• External oscillator or clock source
• Supports inexpensive local crystal
• Minimal board space required
• No external analog loop-filter components required
• Packaged in a 10-pin MSOP
• CS2300 has internal LCO for reference clock
• CS2200 is a subset and consists of clock generation
• CS2100 is a subset and consists of clock multiplication

Diagram

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