CS35L00/01/03

• Hybrid Class-D Architecture
• 1 x 2.9 W into 4 Ω (10% THD+N)
• 1 x 2.3 W into 4 Ω (1% THD+N)
• 1 x 1.7 W into 8 Ω (10% THD+N)
• 1 x 1.4 W into 8 Ω (1% THD+N)
• Ultra-low Power Consumption
• <1 mA Quiescent Current
• Advanced ΔΣ Closed-loop Modulation
• 97 dB Signal-to-Noise Ratio (A-Weighted)
• 0.02% THD+N @ 1 W (SD & HD Mode)
• -85 dB Power Supply Rejection Ratio @ 217Hz
• -70 dB Common Mode Rejection Ratio
• Integrated Protection and Automatic Recovery for Output Short-circuit and Thermal Overload
• Pop and Click Suppression
• Available in Low-profile 10-pin DFN or 9-ball WLCSP
• CS35L00: +6 dB or +12dB Selectable Gain
• CS35L01: +6 dB default Gain
• CS35L03: +12 dB default Gain

Related Documents

• CS35L01/03 Product Datasheet
  7/2011, DS909F1 : 540 Kb
• Errata: CS35L01/03 Rev B0 Silicon
  7/2011, ER909B0R1 : 26 Kb
• CS35L00 Product Datasheet
  2/2011, DS906PP1 : 731 Kb
• Errata: CS35L00 Rev B0 Silicon
  2/2011, ER906PP1 : 30 Kb
• CS35L00/01/03 Product Bulletin
  7/2010, 823111-0610-PB : 2211 Kb

Design Resources

• Smartphone Application Page
  
• 1 x 1.7 W CS35L01 Amplifier Reference Design Kit (4 boards) Datasheet
  6/2010, DS914RD2 : 427 Kb
• 2.7 W x 4 CS35L00 Amplifier Demonstration Board Datasheet
  6/2010, DS913DB2 : 376 Kb
• Unleashing the Audio Potential of Smartphones
  6/2010, 1033 Kb