FREMONT, Calif. - Nov. 8, 1999 -- Leveraging Leveraging six generations of CMOS read channel development, Cirrus Logic Inc. (NASDAQ:CRUS) today announced a new 550 Mbps(2), enhanced 0.25-micron, CMOS read channel (SH3365) for the desktop hard disk drive (HDD) market. The SH3365 CMOS read channel combines patented Partial-Response-Maximum-Likelihood (PRML) technology with a new proprietary advanced detector architecture, enabling drive manufacturers to deliver 15 gigabyte and greater per platter desktop HDDs as early as the second quarter of calendar year 2000.

"With the desktop HDD market in the midst of a dramatic increase in areal density, coupled with a spindle speed transition from 5400 to 7200 rpm, customers are demanding increases in both bit error and data transfer rates," said Peter Hillen vice president of marketing for Cirrus Logic's Magnetic Storage Division. "Our new read channel deploys our patented CC2 coding algorithm to ensure exceptional bit error rate performance and, at 550 Mbps, is one of the industry's fastest quarter-micron read channel cores, making it ideal for next generation desktop HDDs."

New Channel Fosters Capacity & Spindle Speed Increases

As the desktop HDD market transitions from 5400 to 7200 rpm drives and capacity continues to increase, the ability to extract the data signal from noise without error becomes even more difficult. To minimize these errors and provide unsurpassed data integrity, Cirrus Logic's storage science experts, the pioneers of partial-response-maximum-likelihood (PRML) read channels(3), have created a new patented CC2 PRML algorithm. The CC2 algorithm adds redundant bits to the data stream on the fly, resulting in improved detector performance in the presence of certain types of transition noise common in high-density applications. Coupled with an advanced 16-state Viterbi detector, this patented technique offers drive manufacturers as much as a 15-percent capacity increase over Enhanced Partial Response Type 4 (EPR4) read channels.

Enabling Highest User Densities For Desktop Drives

The SH3365 selectable rate RLL encoder/decoder may be programmed for 24/25, 48/51 or 48/52 (d=0) rate codes, depending on the number of redundant bits desired. Adding redundant bits on the fly increases performance at higher user bit densities. Further supporting high densities, with their attendant higher soft error rates, is the error tolerant data sync mark circuitry. This proprietary circuitry contains an optional dual sync mark capability that requires no change to the hard disk controller. Higher density translates directly to increased platter capacity.

550 Mbps System-On-Chip Solution

This announcement also highlights the company's commitment to make core elements simultaneously available for integration into its 3Ci™ platform. The 3Ci system-on-chip provides all the key HDD functions, including the PRML read channel for reliable data acquisition at 550 Mbps; an ARM 32-bit processor core to handle both system and servo control functions and a Ultra ATA 66 or 1394 compatible hard disk controller that links the device to either the PC or consumer devices. Since the 3Ci chip also integrates the customer's servo logic and the ARM processor program memory, the only system functions needed to create a complete HDD design are the pre-amp, motor drivers and buffer memory.

"Integration is the name of the game in HDD electronics," said Hillen. "We realized early on that the key to creating a system-on-chip HDD solution is the ability to successfully design and manufacture all of the subsystem functions in standard CMOS. We continue to build on our leadership position as the only supplier of single-chip HDD solutions by offering standalone and integration core components simultaneously, enabling our customers to reach their time-to-market goals with an integrated solution."

Experienced System-Level Design Support

With six generations of CMOS read channel design, Cirrus Logic offers HDD manufacturers a comprehensive suite of proven evaluation and development tools. In addition, Cirrus Logic supports its customers worldwide with one of the industry's most experienced system and field application teams.

Price & Availability

The SH3365 is manufactured using state-of-the-art 0.25-micron CMOS technology. The new PRML read channel is scheduled for full-volume production in the second quarter of calendar year 2000. Production units will be priced at $6 each in quantities of 100,000.

Cirrus Logic, Inc.

Cirrus Logic is a premier supplier of high-performance analog circuits and advanced mixed-signal chip solutions. The company's products, sold under its own name and the Crystal product brand, enable system-level applications in mass storage, audio and precision data conversion. Additional information about Cirrus Logic is available at www.cirrus.com.

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(1) Cirrus Logic's 3Ci platform won EDN Magazine's 1998 Digital IC Innovation of the Year Award

(2) Read channel data transfer rate reflects worst-case drive environment. Typical data rate at nominal voltage and temperature is up to 650Mbps

(3) Cirrus Logic introduced the first partial-response-maximum-likelihood, CMOS read channel to the desktop HDD market in 1993

Note to editors: Cirrus Logic is a registered trademark and 3Ci is a trademark of Cirrus Logic Inc. All other product names noted herein may be trademarks of their respective holders.